7585 Commits

Author SHA1 Message Date
Andrew Kelley ef2c19d3c1 closer to linking
next problem is there needs to be a namespace because it's needed for
getting the file, for debug info source location purposes.
2022-02-06 23:48:51 -07:00
Andrew Kelley 8a545069a4 hello-world.c is producing Zig AIR 2022-02-06 23:25:08 -07:00
Andrew Kelley 376d443ae3 add Aro as a C frontend
Problems to solve in this branch before merging:

 * Liveness and AIR printing want a ZIR instance. This issue is
   addressed by #10784.
 * linker: updateFunc / updateDecl want a Module instance which
   currently represents only Zig code. These functions should be changed
   to accept a Compilation, not a Module. The relevant state that it
   needed to touch on Module should be moved to Compilation instead.
 * `Decl` needs to be shared by both the C frontend and the Zig
   frontend. It currently has Zig-only fields and the functions to
   create Decl objects don't really fit the API that the C frontend
   needs.
 * A lot of the incremental compilation infrastructure doesn't quite
   match up, for example Decl objects being owned by Namespaces which is
   a Zig concept. Maybe there could be 1 Namespace globally across all C
   files and 1 more Namespace per C file for functions and globals
   declared `static`.
 * There is common code to be extracted from Sema that is shared with
   Aro frontend. All the helper functions having to do with the
   air_instructions and air_extra arrays.

There are many instances of calling `@panic("TODO")` that need to be
cleaned up.

There is a lot of compiler options that Zig is not communicating to Aro,
for example we do not pass the -D switches that we pass to Clang yet.
Need to audit `addCCArgs` and do the equivalent things for setting up
the Aro Compilation.

The Aro code is copied from https://github.com/Vexu/arocc, commit
7a0e54227e1ea2b2df8aa7bd2b7075f735109317. The only patches are to delete
Codegen and replace it with our own, and to delete main.zig, and add
Type and Value to lib.zig.

I believe the current plan is for main Aro development to happen
upstream on the arocc repository and periodically sync it downstream
with the Zig repository. It's up to @Vexu whether to keep that process
or change it in the future.
2022-02-04 19:42:03 -07:00
joachimschmidt557 04f379dd41 stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4
In these cases, the AIR inst can be lowered to only one ldr
instruction.

Also fixes shifts in arm.bits.Offset
2022-02-04 21:07:10 +01:00
Andrew Kelley 95fbce2b95 Sema: fixes to fieldVal, resolveStructFully, Type.eql
fieldVal handles pointer to pointer to array. This can happen for
example, if a pointer to an array is used as the condition expression of
a for loop.

resolveStructFully handles tuples (by doing nothing).

fixed Type comparison for tuples to handle comptime fields properly.
2022-02-03 23:59:32 -07:00
Mateusz Radomski 1b6a1e691f Sema: check for NaNs in cmp (#10760) 2022-02-04 00:58:27 -05:00
Andrew Kelley 0893326e0e Sema: slice improvements
* resolve_inferred_alloc now gives a proper mutability attribute to the
   corresponding alloc instruction. Previously, it would fail to mark
   things const.
 * slicing: fix the detection for when the end index equals the length
   of the underlying object. Previously it was using `end - start` but
   it should just use the end index directly. It also takes into account
   when slicing a comptime-known slice.
 * `Type.sentinel`: fix not handling all slice tags
2022-02-03 21:05:10 -07:00
Andrew Kelley 71e0cca7a7 Merge pull request #10780 from Luukdegram/wasm-behavior-tests
stage2: Wasm - Account for stack alignment
2022-02-03 20:23:46 -05:00
Jakub Konka 4ca9a8d192 x64: implement storing to MCValue.memory for PIE targets 2022-02-04 00:37:43 +01:00
Luuk de Gram 588b88b987 Move passing behavior tests
Singular tests (such as in the bug ones) are moved to top level with exclusions for non-passing backends.
The big behavior tests such as array_llvm and slice are moved to the inner scope with the C backend disabled.
They all pass for the wasm backend now
2022-02-03 22:31:29 +01:00
Luuk de Gram e35414bf5c wasm: Refactor stack to account for alignment
We now calculate the total stack size required for the current frame.
The default alignment of the stack is 16 bytes, and will be overwritten when the alignment
of a given type is larger than that.

After we have generated all instructions for the body, we calculate the total stack size
by forward aligning the stack size while accounting for the max alignment.
We then insert a prologue into the body, where we substract this size from the stack pointer
and save it inside a bottom stackframe local. We use this local then, to calculate
the stack pointer locals of all variables we allocate into the stack.

In a future iteration we can improve this further by storing the offsets as a new `stack_offset` `WValue`.
This has the benefit of not having to spend runtime cost of storing those offsets, but instead we append
those offsets whenever we need the value that lives in the stack.
2022-02-03 21:53:48 +01:00
Luuk de Gram ae1e3c8f9b wasm: Implement vector_init for array & structs
Implements the instruction `vector_init` for structs and arrays.
For arrays, it checks if the element must be passed by reference or not.
When not, it can simply use the `offset` field of a store instruction to copy the values
into the array. When it is byref, it will move the pointer by the element size, and then perform
a store operation. This ensures types like structs will be moved into the right position.
For structs we will always move the pointer, as we currently cannot verify if all fields are
not by ref.
2022-02-03 21:43:25 +01:00
Luuk de Gram 29013220d9 wasm: Implement elem_ptr
This implements lowering elem_ptr for decl's and constants.
To generate the correct pointer, we perform a relocation by using the addend
that represents the offset. The offset is calculated by taking the element's size
and multiplying that by the index.

For constants this generates a single immediate instruction, and for decl's
this generates a single pointer address.
2022-02-03 21:42:48 +01:00
Jakub Konka 3832b58229 Merge pull request #10775 from ziglang/x64-freeze-api
stage2: migrate x64 to freeze regalloc API, and remove the concept of register exceptions
2022-02-03 20:12:35 +01:00
Jakub Konka 228b798af5 elf: generated DWARF debug info for named structs 2022-02-03 18:47:36 +01:00
Jakub Konka 74a01e3d64 stage2: remove the concept of register exceptions 2022-02-03 18:08:29 +01:00
Jakub Konka e0b1170b67 x64: swap out register exceptions for freeze/unfreeze api 2022-02-03 17:55:22 +01:00
Jakub Konka f4e0641450 x64: use freeze/unfreeze api; TODO for PIE 2022-02-03 14:31:16 +01:00
Jakub Konka e52af26856 Merge branch 'test-1486' of git://github.com/mparadinha/zig into mparadinha-test-1486 2022-02-03 14:00:28 +01:00
Jakub Konka b77757fe39 elf: add basic handling of .data section 2022-02-03 08:47:06 +01:00
Andrew Kelley 557a097523 CLI: link_libcpp implies link_libc
Improves a warning message for some cases of using `zig run -lc++`.
2022-02-02 14:54:14 -07:00
Jakub Konka 7694361832 Merge pull request #10769 from ziglang/link-lib-fixes
stage2: handle name-qualified imports in sema, add a zerofill sections workaround to incremental macho
2022-02-02 20:59:17 +01:00
Andrew Kelley 3eb8d01f52 Merge pull request #10766 from ziglang/yeet-anytype-fields
remove anytype fields from the language
2022-02-02 13:39:27 -05:00
Jakub Konka 06a037bb95 macho: handle bss like normal section in stage2
This is just a temporary workaround until I work out how to manage
non-physical sections between stage2 incremental updates.
2022-02-02 16:22:58 +01:00
Jakub Konka 380462ffc0 sema: do not pass libc or libc++ to the linker 2022-02-02 15:33:38 +01:00
Jakub Konka c157b19878 wasm32: fix struct padding 2022-02-02 13:43:46 +01:00
Jakub Konka 15ff891f04 stage2: pad out (non-packed) struct fields when lowering to bytes
* pad out (non-packed) struct fields when lowering to bytes to be
  saved in the binary - prior to this change, fields would be
  saved at non-aligned addresses leading to wrong accesses
* add a matching test case to `behavior/struct.zig` tests
* fix offset to field calculation in `struct_field_ptr` on `x86_64`
2022-02-02 13:43:41 +01:00
Jakub Konka 0cccd8a887 x86_64: handle struct_field_ptr for stack_offset mcv 2022-02-02 10:48:21 +01:00
Jakub Konka 9de30bb065 x86_64: handle struct_field_ptr for register mcv 2022-02-02 10:48:21 +01:00
Jakub Konka 09e69c8c77 x86_64: start moving to new regalloc freeze API 2022-02-02 10:48:21 +01:00
mparadinha ef4c54ba38 need to go through the GOT, and use a temporary register 2022-02-02 09:24:39 +00:00
mparadinha b67b89025c implement store for 8 byte immediates 2022-02-02 08:50:37 +00:00
mparadinha cc16ac9314 implement storing to MCValue.memory 2022-02-02 08:50:37 +00:00
Andrew Kelley 449554a730 stage2: remove anytype fields from the language
closes #10705
2022-02-01 19:06:40 -07:00
Andrew Kelley f4a249325e stage1: avoid anytype fields for type info
prerequisite for #10705
2022-02-01 18:10:19 -07:00
Andrew Kelley 5cf918143c Sema: remove the data field from TypeInfo.Declaration
stage2 follow-up to aa326328d0
2022-02-01 11:40:29 -07:00
Andrew Kelley 4188d54130 Sema: replace some initTag calls with constants
No functional changes.
2022-02-01 11:37:29 -07:00
Mitchell Hashimoto 970f954039 stage2: cmp_eq between untyped undefines values results in undef bool 2022-02-01 11:21:23 -07:00
Andrew Kelley 3e99495ed8 Merge pull request #10742 from ziglang/ArrayHashMapEql
std: make ArrayHashMap eql function accept an additional param
2022-02-01 13:20:28 -05:00
Andrew Kelley aa326328d0 stage1: remove the data field from TypeInfo.Declaration
Partially implements #10706
2022-01-31 22:09:41 -07:00
Andrew Kelley 39983d7ff5 stage2: update to new ArrayHashMap API 2022-01-31 21:12:37 -07:00
Jakub Konka 627cf6ce48 astgen: clean up source line calculation and management
Clarify that `astgen.advanceSourceCursor` already increments absolute
values of the line and columns numbers; i.e., `GenZir.calcLine` is thus
not only obsolete but wrong by design.

Incidentally, this clean up allows for specifying the `FnDecl` line
numbers for DWARF use correctly as relative values with respect to
the start of the parent `Decl`. This `Decl` in turn has its line number
information specified relatively to its parent `Decl`, and so on, until
we reach the global scope.
2022-01-31 22:29:29 -05:00
Andrew Kelley abbcf40327 Sema: fix index type in AIR being u64 instead of usize 2022-01-31 16:41:14 -07:00
joachimschmidt557 2913950ca9 stage2 ARM: implement ptr_stack_offset function parameters 2022-01-31 23:52:32 +01:00
Andrew Kelley cf88cf2657 std: make ArrayHashMap eql function accept an additional param
which is the index of the key that already exists in the hash map.

This enables the use case of using `AutoArrayHashMap(void, void)` which
may seem surprising at first, but is actually pretty handy!
This commit includes a proof-of-concept of how I want to use it, with a
new InternArena abstraction for stage2 that provides a compact way to
store values (and types) in an "internment arena", thus making types
stored exactly once (per arena), representable with a single u32 as a
reference to a type within an InternArena, and comparable with a
simple u32 integer comparison. If both types are in the same
InternArena, you can check if they are equal by seeing if their index is
the same.

What's neat about `AutoArrayHashMap(void, void)` is that it allows us to
look up the indexes by key, *without actually storing the keys*.
Instead, keys are treated as ephemeral values that are constructed as
needed.

As a result, we have an extremely efficient encoding of types and
values, represented only by three arrays, which has no pointers, and can
therefore be serialized and deserialized by a single writev/readv call.
The `map` field is denormalized data and can be computed from the other
two fields.

This is in contrast to our current Type/Value system which makes
extensive use of pointers.

The test at the bottom of InternArena.zig passes in this commit.
2022-01-31 01:20:45 -07:00
joachimschmidt557 66cf011aa9 stage2 ARM: Move to new regalloc freeze API 2022-01-30 19:41:51 -05:00
Andrew Kelley 227968d78c Merge pull request #10723 from joachimschmidt557/stage2-riscv
stage2 RISCV64: Move to new regalloc freeze API
2022-01-30 19:41:35 -05:00
joachimschmidt557 b2338de7fd stage2 AArch64: Move to new regalloc freeze API 2022-01-30 19:41:11 -05:00
Andrew Kelley fb7060d3c2 stage2: implement shl_exact and shr_exact
These produce an undefined value when one bits are shifted out.

New AIR instruction: shr_exact.
2022-01-30 16:23:31 -07:00
Andrew Kelley 0c30799d40 Sema: fix comptime shl for fixed-width integers 2022-01-30 15:23:40 -07:00