joachimschmidt557 04f379dd41 stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4 ...

In these cases, the AIR inst can be lowered to only one ldr
instruction.

Also fixes shifts in arm.bits.Offset

2022-02-04 21:07:10 +01:00

..

aarch64

stage2: remove the concept of register exceptions

2022-02-03 18:08:29 +01:00

arm

stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4

2022-02-04 21:07:10 +01:00

riscv64

stage2: remove the concept of register exceptions

2022-02-03 18:08:29 +01:00

wasm

Move passing behavior tests

2022-02-03 22:31:29 +01:00

x86

stage2,x86_64: revert fixing callee preserved regs

2021-11-19 22:18:56 +01:00

x86_64

x64: implement storing to MCValue.memory for PIE targets

2022-02-04 00:37:43 +01:00