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synced 2026-05-06 04:16:46 -04:00
tcg: Make TCG_TARGET_REG_BITS common
Since we only support 64-bit hosts, there's no real need to parameterize TCG_TARGET_REG_BITS. It seems worth holding on to the identifier though, for documentation purposes. Move one tcg/*/tcg-target-reg-bits.h to tcg/target-reg-bits.h and remove the others. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
@@ -24,7 +24,7 @@
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#include <ffi.h>
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#pragma GCC diagnostic pop
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#endif
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#include "tcg-target-reg-bits.h"
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#include "tcg/target-reg-bits.h"
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#define MAX_CALL_IARGS 7
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@@ -7,10 +7,10 @@
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#ifndef _ARCH_PPC64
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# error Expecting 64-bit host architecture
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#endif
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/*
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* We only support 64-bit hosts now.
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* Retain the identifier for documentation.
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*/
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#define TCG_TARGET_REG_BITS 64
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#endif
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+1
-1
@@ -31,7 +31,7 @@
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#include "qemu/plugin.h"
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#include "qemu/queue.h"
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#include "tcg/tcg-mo.h"
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#include "tcg-target-reg-bits.h"
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#include "tcg/target-reg-bits.h"
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#include "tcg-target.h"
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#include "tcg/tcg-cond.h"
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#include "tcg/insn-start-words.h"
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@@ -1,12 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Define target-specific register size
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* Copyright (c) 2023 Linaro
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS 64
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#endif
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@@ -1,21 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/*
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* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
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* for the initial upstreaming of this architecture, so don't bother and just
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* support the LP64* ABI for now.
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*/
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#if defined(__loongarch64)
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# define TCG_TARGET_REG_BITS 64
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#else
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# error unsupported LoongArch register size
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#endif
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#endif
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@@ -1,16 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#if !defined(_MIPS_SIM) || _MIPS_SIM != _ABI64
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# error "Unknown ABI"
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#endif
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#define TCG_TARGET_REG_BITS 64
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#endif
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@@ -1,19 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2018 SiFive, Inc
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/*
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* We don't support oversize guests.
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* Since we will only build tcg once, this in turn requires a 64-bit host.
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*/
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#if __riscv_xlen != 64
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#error "unsupported code generation mode"
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#endif
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#define TCG_TARGET_REG_BITS 64
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#endif
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@@ -1,17 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/* We only support generating code for 64-bit mode. */
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#if UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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#else
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# error "unsupported code generation mode"
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#endif
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#endif
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@@ -1,12 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2023 Linaro
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS 64
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#endif
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@@ -1,18 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2009, 2011 Stefan Weil
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#if UINTPTR_MAX == UINT32_MAX
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# define TCG_TARGET_REG_BITS 32
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#elif UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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#else
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# error Unknown pointer size for tci target
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#endif
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#endif
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@@ -1,16 +0,0 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#ifdef __x86_64__
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# define TCG_TARGET_REG_BITS 64
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#else
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# error
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#endif
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#endif
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